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Mobo's RAM and processors functions.......

Postby Huntnsinme » Mon Apr 19, 2004 3:59 am

I fixed it Tweaker thanks man...
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Postby tWeaKmoD » Mon Apr 19, 2004 4:00 am

Huntnsinme wrote:I fixed it Tweaker thanks man...


You can calle me Paul(2)...tweaker just kind of sound werid, but whatever, I've been called worse.
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Postby Huntnsinme » Mon Apr 19, 2004 4:03 am

Aight Paul 2.I am Richard nice to meet you.
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Postby tWeaKmoD » Mon Apr 19, 2004 4:06 am

Huntnsinme wrote:Aight Paul 2.I am Richard nice to meet you.


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Nice to meet you Richard.
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Postby Weaver » Mon Apr 19, 2004 4:09 am

Huntnsinme wrote:
Weaver wrote:
Huntnsinme wrote:zzzzzzzzzzzzzzzzzzzPERK........Thats what I am asking if there would be some sort of bottleneck at the cpu, or chipset.or mobo even?

"The only advice I can offer is that the design of the northbridge accepts only a specified # of slots and their paths are designed into the chip itself,." But can you make the paths accept more data?


Generally no, not without redoing the logic inside the chip itself. If a bus is designed to move data 64 bits at a time, then trying to move 128 bits at a time is going to require more traces or reworked logic in the chip.

I should point out that I am not an expert when it comes to this subject, so don't take my word on it.

-Weaver



Ok I am asking to which chip the logic would have to be redone? The northbridge or the CPU?


First off, you have to realize the question you are asking would something similar to asking a mechanic "How do you make a car faster?"

There are many ways, where do you want to begin?

Most 32 bit CPU's (Athlon XP's & P4's etc) can address 2^32 bytes of information, which turns out to be somewhere in the neighborhood of 4 GiB. If you want more than that, you have to kludge something or redesign the CPU itself. Intel's PAE is one such kludge.

Once the CPU can address more than 2^32 bytes, the memory controller needs to be able to support > 2^32 as well. This means a change to the logic in the memory controller as well.

If you want "faster" memory, there are many options too. You can speed up the modules themselves, either bump up the core frequency that the modules work at or lower the internal latencies (CAS, RAS, etc).

Once the memory controller and the modules are communicating faster (or on wider paths) you still have the memory controller and the CPU to worry about. You can either bump up that core frequency (called the Front Side Bus) or you can increase the bus width.

There are many options and configurations available and it can quickly escalate into a very complex analysis of computer hardware. I only wish I knew more about it so I could better explain it.

-Weaver
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The primary purpose of the DATA statement is to give names to constants; instead of referring to pi as 3.141592653589793 at every appearance, the variable PI can be given that value with a DATA statement and used instead of the longer form of the constant. This also simplifies modifying the program, should the value of pi change.
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Postby imnuts » Mon Apr 19, 2004 4:12 am

i think he might be talking about the cpu, but redoing any of the logic on any of the parts would be virtually impossible as the processes that it takes to put the logic there take a long time and a lot of planning. i know this because we just saw a video about making chips in my one class. And if it took a while back when the films where made (mac os2, 486, ms-dos 6 era) then imagine how long it takes now with the complexity of today's chips
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Postby Huntnsinme » Mon Apr 19, 2004 4:12 am

Wow Weaver. you did pretty good. I just wish I could understand it better.LOL I am going to bed. Thank you I will resume tomorrow.
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